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18-Channel Gamma Buffer with Regulator ADD8708
FEATURES
18 precision gamma reference outputs Mask-programmable gamma resistors: 0.2% resolution and 0.1% accuracy Mask-programmable voltage regulator: 0.4% accuracy Upper 9 buffers swing to VDD Lower 9 buffers swing to GND Single-supply operation: 7.5 V to 16.5 V Gamma current drive: 15 mA per channel Peak output current: 150 mA Output voltage stable under load conditions Pin-to-pin compatible with ADD8709 48-lead, Pb-free LQFP and LFCSP
FUNCTIONAL BLOCK DIAGRAM
MASK-PROGRAMMABLE REGULATOR RESISTORS FB 700* VREG OUT VDD VDD
GND + - GAMMA BUFFERS
1.2V 700* VIN18 700* VIN17 700* VIN16 700* VIN15 700* VIN14 700* VIN13
VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1
APPLICATIONS
LCD TV panels LCD monitor panels
GENERAL DESCRIPTION
The ADD8708 is an 18-channel integrated gamma reference for use in high resolution LCD TV and monitors panels. The output buffers feature high current drive and low offset voltage to provide an accurate and stable gamma curve. The top nine channels swing to VDD; the lower nine channels swing to GND. Integrating the gamma setup resistors drastically reduces the external component count while increasing the gamma curve accuracy. To accommodate multiple column drivers and panel architectures, the ADD8708 is mask programmable to a 0.2% resolution using the on-chip 500 resistor string. An on-board voltage regulator provides a fixed input for the resistor string, isolating the gamma curve from the supply ripple. The ADD8708 is specified over the temperature range of -40C to +105C and comes in both a 48-lead, Pb-free, lead-frame chip-scale package and a Pb-free, low-profile, quad flat package.
700* VIN12 700* VIN11 700* VIN10 700* VIN9 700* VIN8 700* VIN7 700* VIN6 700* VIN5 700* VIN4 700* VIN3 700* VIN2 700* VIN1 MASK-PROGRAMMABLE RESISTOR STRING *ESD PROTECTION RESISTORS GND GND
Figure 1. 48-Lead LQFP or LFCSP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
04614-001
ADD8708 TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 7 Application Notes ........................................................................... 10 Tap Point Selection..................................................................... 10 Voltage Regulator ....................................................................... 11 Maximum Power Dissipation ................................................... 11 Land Pattern................................................................................ 11 Operating Temperature Range ................................................. 12 Typical Applications Circuit.......................................................... 14 Tap Point and Regulator Voltage Request Form......................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide........................................................................... 16
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADD8708 ELECTRICAL CHARACTERISTICS
VDD = 16 V, TA @ 25C, unless otherwise noted. Table 1.
Parameter GAMMA CURVE CHARACTERISTICS Accuracy Programming Resolution Total Resistor String BUFFER CHARACTERISTICS OUTPUTS Output Voltage Range (Ch18 to Ch10) Output Voltage Range (Ch9 to Ch1) Output vs. Load (Ch18, Ch17, Ch2, Ch1) Output vs. Load (Ch16 to Ch3) INPUTS Offset Voltage Offset Voltage Drift Input Bias Current Input Voltage Range (Ch18 to Ch10) Input Voltage Range (Ch9 to Ch1) DYNAMIC PERFORMANCE Slew Rate Bandwidth Settling Time to 0.1% Phase Margin Power Supply Rejection Ratio VOLTAGE REGULATOR Programmable Range Initial Regulator Accuracy Dropout Voltage Line Regulation Load Regulation Maximum Load Current Feedback Reference Voltage Feedback Input Bias Current SYSTEM ACCURACY Total Error3, 4 POWER SUPPLY Supply Voltage Supply Current Symbol RACC1 RRES RTOTAL Conditions Min Typ 0.1 0.2 15 Max 0.4 Unit % % k
500 segments
VOUT VOUT VOUT2 VOUT2 VOS VOS/T IB VIN VIN SR BW tS o PSRR
IL = 100 A IL = 100 A IL = 20 mA IL = 5 mA
1.4 0 15 5 5 20 0.5 1.4 0
VDD VDD - 1.4
V V mV mV mV V/C A V V V/s MHz s Degrees dB
15 1.5 VDD VDD - 1.4
-40C TA +105C -40C TA +105C
RL = 10 k, CL = 200 pF -3 dB, RL = 10 k, CL = 200 pF 1 V, RL = 10 k, CL = 200 pF RL = 10 k, CL = 200 pF VDD = 7 V to 17 V, -40C TA +105C
4
68
6 4.5 1.1 55 90
VREG OUT VACC VDO REGLINE REGLOAD IO VREF IB FB VTotal Error VDD ISY
5 No load; VREG OUT = 14.4V IL = 100 A IL = 5 mA VIN = 8.5 V to 16.5 V, VOUT = 8 V IO = 100 A to 10 mA -40C TA +105C -40C TA +105C -40C TA +105C 7.5 No load; -40C TA +105C 9.5 0.4 100 310 0.01 0.02 5 -150 1.2 10 0.5
VDD - 0.6 1.5 150 350 0.20 0.10
V % mV mV %/V %/mA mA V nA % V mA
150 3 16 16
1 2 3
Gamma curve accuracy includes resistor matching and buffer errors, but excludes the regulator error. VOUT is the shift from the desired output voltage under the specified current load. Total error is the difference between the designed and actual output voltage divided by the actual regulator output voltage or full-scale voltage. 4 Total error includes regulator error, resistor string error, bias current effects, and buffer offset voltage.
Rev. 0 | Page 3 of 16
ADD8708 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (VDD) Input Voltage Storage Temperature Range Operating Temperature Range1 Junction Temperature Range Lead Temperature Range (Soldering, 60 sec) ESD Tolerance (HBM) ESD Tolerance (MM) Rating 18 V -0.5 V to VDD -65C to +150C -40C to +105C -65C to +150C 300C 1500 V 200 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. Package Characteristics
Package Type LFCSP (CP) LQFP (ST) JA2 28.3 N/A JA3 47.7 74.57 Unit C/W C/W
1 2
See the Application Notes section. JA for exposed pad soldered to JEDEC 4-layer board. 3 JA for exposed pad not soldered down.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADD8708 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12
38
48
47
46
45
44
43
42
41
40
39
37 36 35 34 33 32
REGFB GND VDD VREG OUT VIN18 VIN17 VIN16 VIN15 VIN14
VOUT11
GND
VDD
GND
VDD
1 2 3 4 5 6 7 8 9
VOUT10 VOUT9 VOUT8 VOUT7 VDD GND VOUT6 VOUT5 VOUT4 VOUT3 VOUT2
04614-002
ADD8708
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
VIN13 10 VIN12 11 VIN11 12
13 14 15 16 17 18 19 20 21 22 23 24
VOUT1
VIN9
VIN8
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN10
VIN1
GND
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name REGFB GND VDD VREG OUT VIN18 VIN17 VIN16 VIN15 VIN14 VIN13 VIN12 VIN11 VIN10 VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 GND VDD Description Regulator Feedback. Compares a percentage of the regulator output to the internal 1.2 V voltage reference. Internal resistors are used to program the desired regulator output voltage. Ground. Normally 0 V. Supply Voltage. Normally 16 V. Regulator output voltage. Provides reference voltage to resistor string and is internally connected to the top of the resistor string.
Buffer inputs. Normally floating.1
Ground. Normally 0 V. Supply Voltage. Normally 16 V.
1
External resistors can be added to modify the internal resistor string to change the gamma voltage. An external resistor calculator is available upon request from your local sales office.
Rev. 0 | Page 5 of 16
VDD
ADD8708
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 GND VDD VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 GND VDD VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 GND VDD Description
Buffer Outputs. These buffers can swing to ground.
Ground. Normally 0 V. Supply voltage. Normally 16 V. Buffer Output. These buffers can swing to ground.
Buffer Output. These buffers can swing to VDD. Ground. Normally 0 V. Normally 16 V.
Buffer Outputs. These buffers can swing to VDD.
Ground. Normally 0 V. Supply voltage. Normally 16 V.
Rev. 0 | Page 6 of 16
ADD8708 TYPICAL PERFORMANCE CHARACTERISTICS
20 15 ISINK = 25mA ISINK = 15mA ISINK = 5mA 25
OUTPUT VOLTAGE ERROR (mV)
OUTPUT VOLTAGE ERROR (mV)
10 5 0 ILOAD = 0mA -5 -10 -15 -20 -25 -30 -35 -20 -10 0 10 ISOURCE = 25mA ISOURCE = 15mA ISOURCE = 5mA 20 30 40 50 60 70 TEMPERATURE (C) 80
20 CH3 SOURCE 15 CH3 SINK CH9 SINK 10 CH9 SOURCE
5
04614-006
04614-003
90 100 110 120
0 0.1
1 10 LOAD CURRENT (mA)
100
Figure 3. Output Voltage Error vs. Temperature
30
Figure 6. Output Voltage Error vs. Load Current (Channels 3 and 9)
25
OUTPUT VOLTAGE ERROR (mV)
OUTPUT VOLTAGE ERROR (mV)
25 CH17 SOURCE 20 CH18 SOURCE 15
20 CH1 SOURCE 15 CH1 SINK
CH2 SOURCE CH2 SINK
10
10 CH18 SINK 5
04614-004
5
04614-007
CH17 SINK 0 0.1 1 10 LOAD CURRENT (mA)
100
0 0.1
1 10 LOAD CURRENT (mA)
100
Figure 4. Output Voltage Error vs. Load Current (Channels 17 and 18)
30
Figure 7. Output Voltage Error vs. Load Current (Channels 1 and 2)
11 10 10V PULSE 120pF 320pF 520pF 1nF 10nF
OUTPUT VOLTAGE ERROR (mV)
25
9 8
AMPLITUDE (V)
CH10 SOURCE CH16 SOURCE CH10 SINK
20
7 6 5 4 3 2
15
10
5
04614-005
CH16 SINK 0 0.1 1 10 LOAD CURRENT (mA)
1 0 -200 0 200 400
100
600 800 1000 1200 1400 1600 1800 TIME (ns)
Figure 5. Output Voltage Error vs. Load Current (Channels 10 and 16)
Figure 8. Gamma Buffers Transient Load Response vs. Capacitive Loading
Rev. 0 | Page 7 of 16
04614-008
ADD8708
1000 900 800 0 100 200
DROPOUT VOLTAGE (mV)
04614-009
NUMBER OF AMPLIFIERS
700 600 500 400 300 200 100 0 -0.30 -0.18 -0.10 -0.02 0.06 0.14 0.22 0.30 GAMMA OUTPUT ERROR DUE TO OFFSET AND RESISTOR MATCHING (% OF FS)
300 400 500 600 700 800 900 1000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OUTPUT CURRENT (mA)
04614-012
Figure 9. Gamma Output Voltage Error
0.3 MAX ERROR EACH STEP 0.2 TYPICAL UNIT B 0.1 800 750 700 650
Figure 12. Dropout Voltage vs. Output Current
10mA
DROPOUT VOLTAGE (mV)
TYPICAL UNIT C
600 550 500 450 400 350 300 250 200
04614-013
ERROR (%)
5mA
0 TYPICAL UNIT A -0.1
-0.2
04614-010
MIN ERROR EACH STEP -0.3 0 1 2 3 4 5 6 7 8 OUTPUT CHANNEL 9 10 11 12
150 100 50 0 -25 -15 -5 5 15 25 35 45 55 65 TEMPERATURE (C) 75 85
0mA
95 105 115
Figure 10. Gamma Output Error per Channel (920 Parts)
15 14 13 12 11 10 9 8 7 6 5 4 3
04614-011
Figure 13. Dropout Voltage vs. Temperature
14.5 14.4 -20C 14.3
REGULATOR OUTPUT (V)
OUTPUT VOLTAGE (V)
ILOAD = 0mA ILOAD = 5mA
14.2 14.1 14.0 +85C 13.9 +95C 13.8 +105C 13.7 13.6 0 2 4 6 8 10 12 14 LOAD CURRENT (mA) 16 +25C +55C
0C
ILOAD = 10mA
1 0 17 16 15 14 13 12 11 10 9 8 7 6 INPUT VOLTAGE (V) 5 4 3 2 1 0
18
20
Figure 11. Dropout Characteristics
Figure 14. Regulator Output vs. ILOAD over Temperature
Rev. 0 | Page 8 of 16
04614-014
2
ADD8708
14.45 0mA 14.40
12 11 10
REGULATOR OUTPUT (V)
SUPPLY CURRENT (mA)
04712-0-021
5mA
9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 18
04614-018
14.35
14.30 10mA 14.25
14.20 -20 -10
0
10
20
30 40 50 60 70 TEMPERATURE (C)
80
90 100 110
Figure 15. Regulator Output vs. Temperature
18 CLOAD = 1F 11.0
Figure 18. Supply Current vs. Supply Voltage
SUPPLY CURRENT (mA)
17
400 200
OUTPUT VOLTAGE CHANGE (mV)
10.9
INPUT VOLTAGE (V)
10.8
16
0 -200
10.7
10.6
15
-400
10.5
04614-016 04614-019
14 TIME (100s/DIV)
10.4 -20
0
20
40 60 TEMPERATURE (C)
80
100
120
Figure 16. Regulator Line Transient Response
Figure 19. Supply Current vs. Temperature
CLOAD = 1F 40 20
0 -20 -40 0.1
TIME (100s/DIV)
Figure 17. Regulator Load Transient Response
Rev. 0 | Page 9 of 16
04614-017
5
OUTPUT VOLTAGE CHANGE (mV)
LOAD CURRENT (mA)
ADD8708 APPLICATION NOTES
The ADD8708 is a mask-programmable gamma reference generator that allows source drivers to be optimized for the different combinations of liquid crystals, glass sizes, etc. in large LCD panels. It generates 18 gamma reference outputs that can be mask-programmed in 0.2% increments using the 500 matched internal resistors (see Figure 20), so that every point on the curve can be targeted within 0.1% of the desired value.
TAP POINT 4 TAP POINT 3 TAP POINT 2 TAP POINT 1 TAP POINT 500 TAP POINT 499 TAP POINT 498 TAP POINT 497
TAP POINT SELECTION
The ADD8708 uses a single resistor string consisting of 500 individual elements. The tap points are mask programmable and completely independent of each other. See the Tap Point and Regulator Voltage Request Form in this data sheet.
VREG OUT 500-TPX VINX TPX VOUTX
04614-022
Figure 22. Gamma Buffers Tap Point Circuit
Tap point voltages can be derived from the following equation:
VOUT X = TPX x VREG 500
OUT
EACH R = 30 TYPICALLY
04614-020
Figure 20. 500 Mask-Programmable Resistor String
where TPX is the desired tap point for the Xth channel.
In a typical panel application, the selected source drivers have an internal gamma curve that is not ideal for the specific panel (see Figure 21). The ADD8708 allows the gamma curve in the source drivers to be adjusted appropriately, and also ensures that all the source drivers have the same gamma curve.
16 14 12
Table 5. Typical Mask Implementation1 VDD = 16 V, VREG OUT = 14.4 V, 0 X 500
VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 Tap Point (X) 500 396 369 361 354 350 341 317 299 225 211 177 167 163 154 146 118 7 Voltage 14.400 11.405 10.627 10.397 10.195 10.080 9.821 9.130 8.611 6.480 6.077 5.098 4.810 4.694 4.435 4.205 3.398 0.202 Units V V V V V V V V V V V V V V V V V V
GAMMA VOLTAGE (V)
10 8 ORIGINAL GAMMA CURVE IN SOURCE DRIVERS 6 PANEL GAMMA CURVE CORRECTED BY ADD8708 4
04614-021
2 0 GAMMA REFERENCE INPUT POINTS
Figure 21. Original and Corrected Gamma Curves
The matching and tracking accuracy of the internal resistors is typically 0.1% with worst-case deviation from the desired curve within 0.4% of the ideal gamma curve, over temperature. The ADD8708 also includes a low-dropout linear regulator to provide a stable reference level for the gamma curve for optimum panel performance.
_______________________________
1
ADD8708 release samples do not have these typical values. The values on the samples are nonmonotonic and can be provided upon request.
Rev. 0 | Page 10 of 16
ADD8708
VOLTAGE REGULATOR
The on-board voltage regulator provides a regulated voltage to the resistor chain to provide stable gamma voltages. The two mask-programmable internal resistors, R1 and R2, and a reference voltage set the output of the regulator. The typical values of these parts are shown in Figure 23. In addition, see the Tap Point and Regulator Voltage Request Form in this data sheet.
R1 5k R2 55k
LAND PATTERN
The LFCSP package comes with a thermal pad. Soldering down this thermal pad dramatically improves the heat dissipation of the package. It is necessary to attach vias that connect the soldered thermal pad to another layer on the board. This provides an avenue to dissipate the heat away from the part. Without vias, the heat is isolated directly under the part. Subdivide the solder paste, or stencil layer, for the thermal pad to reduce solder balling and splatter. It is not critical how the subdivisions are arranged, as long as the total coverage of the solder paste for the thermal pad is greater than 50%. The land pattern is critical to heat dissipation. A suggested land pattern is shown in Figure 22. The thermal pad is attached to the substrate. In the ADD8708, the substrate is connected to VDD. To be electrically safe, the thermal pad should be soldered to an area on the board that is electrically isolated or connected to VDD. Attaching the thermal pad to ground adversely affects the performance of the part.
VREG OUT VREF 1.2V + -
04614-023
Figure 23. Voltage Regulator
The internal resistors have a typical accuracy of 0.1%. External resistors can be used to adjust the regulator voltage; however, it is not recommended. Please contact your local sales office for further details.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADD8708 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADD8708. Exceeding a junction temperature of 175C for an extended period can result in changes in the silicon devices, potentially causing failure.
Rev. 0 | Page 11 of 16
ADD8708
OPERATING TEMPERATURE RANGE
The junction temperature is as follows: TJ = TAMB + JA x PDIS where: TAMB = ambient temperature. JA = junction-to-ambient thermal resistance, in C/watt. PDIS = power dissipated in the device, in watts. For the ADD8708, PDIS can be calculated by this equation: PDIS = VDD x IDQ + (IOUT X(+) x (VDD - VOUT X)) + (-IOUT X(-) x VOUT X) + (VDD - VREG OUT ) x ILOAD where: VDD x IDQ = nominal system power requirements. IOUT X(+) x (VDD - VOUT X)= positive-current amplifier load power dissipation (current comes from VDD). -IOUT X(-) x VOUT X = negative-current amplifier load power dissipation (current goes to GND). (VDD - VREG OUT) x ILOAD = regulator load power dissipation. In this example, TAMB = 95C. To calculate PDIS, assume the values in Table 6. Table 6.
VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT X (V) 14.400 11.405 10.627 10.397 10.195 10.080 9.821 9.130 8.611 6.480 6.077 5.098 4.810 4.694 4.435 4.205 3.398 0.202 IOUT X (mA) 4.3 5.2 -4.4 7.3 7.6 -3.9 8.3 7.9 -4.5 -4.2 5.6 -3.3 -6.9 5.7 3.5 9.6 -9.5 -7.2 P (W) 0.00688 0.0239 0.0468 0.0409 0.0441 0.0393 0.0513 0.0543 0.0389 0.0272 0.0556 0.0168 0.0332 0.0644 0.0405 0.113 0.0323 0.00145 0.731
VDD x IDQ = 16 V x 15 mA = 0.240 W (VDD - VREG OUT) x ILOAD = (16 V - 14.4 V) x 5 mA = 0.008 W PDIS = 0.240 W + 0.731 W + 0.008 W =0.979 W
Example 1
Exposed pad soldered down with via JA = 28.3C/W: TJ = 95C + (28.3C/W) x (0.979 W) = 122.7C where 150C is the maximum junction temperature that is guaranteed before the part breaks down. The maximum process limit is 125C. Because TJ is < 150C and < 125C, this example demonstrates a condition where the part should perform within process limits.
Example 2
Exposed pad not soldered down JA = 47.7C/W: TJ = 95C + (47.7C/W) x (0.979 W) = 141.7C In this example, TJ is < 150C but > 125C. Although the part should not exhibit any damage in this situation, the process limits have been exceeded. The part may no longer operate as intended. These examples show that soldering down the exposed pad is important for proper heat dissipation. Under the same powerup and loading conditions, the unsoldered part has a higher temperature than the soldered part. Therefore, it is strongly advised that the exposed pad be soldered to VDD to maintain part integrity.
(IOUT X(+) x (VDD - VOUT X)) + (-IOUT X(-) x VOUT X)
Rev. 0 | Page 12 of 16
ADD8708
7.31mm HEAT SINK SOLDER PASTE AREA 5.40mm
1.90mm
1.60mm 5.93mm
5.78mm
0.69mm 0.5mm 0.075mm 0.075mm 0.33mm DIAMETER THERMAL VIA 0.28mm
04614-024
1.60mm
Figure 24. 48-Pin LFCSP (CP-48) Land Pattern--Dimensions Shown in Millimeters
Notes: 1. 2. 3. 4. Areas in black represent the board metallization. Areas in white represent the solder mask and vias. Hatched area is for the heat sink solder paste. The thermal pad is electrically active. The solder mask opening should be 0.150 mm larger than the pad size, resulting in 0.075 mm of clearance between the copper pad and solder mask.
Rev. 0 | Page 13 of 16
ADD8708 TYPICAL APPLICATIONS CIRCUIT
VREG OUT VDD NORMALLY FB OPEN ESD PROTECTION RESISTOR 5k 700 55k 0.1F 0.1F
GAMMA 18 GAMMA 17 GAMMA 16 GAMMA 15 GAMMA 14 GAMMA 13 GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
16V
1.2V
+ -
VOLTAGE REGULATOR 0 TP18 = 500
GAMMA BUFFERS VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 14.400V
VIN18 VIN17 VIN16 VIN15 VIN14 VIN13 VIN12 VIN11 VIN10 NORMALLY OPEN VIN9 VIN8 VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1
700 TP17 = 396 700 TP16 = 369 700 TP15 = 361 700 TP14 = 354 700 TP13 = 350 700 TP12 = 341 700 TP11 = 317 700 TP10 = 299 700 TP9 = 225 700 TP8 = 211 700 TP7 = 177 700 TP6 = 167 700 TP5 = 163 700 TP4 = 154 700 TP3 = 146 700 TP2 = 118 700 TP1 = 7 700 ESD PROTECTION RESISTORS
3.12k
11.405V
810
10.627V
240
10.397V
GAMMA 18 GAMMA 17 GAMMA 16 GAMMA 15 GAMMA 14 GAMMA 13 GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
210
10.195V
120
10.080V
270
9.821V
720
9.130V
540
8.611V
2.22k
6.480V
420
6.077V
1.02k
5.098V
300
4.810V
120
4.694V
270
4.435V
240
4.205V
840
3.398V
3.33k 210
0.202V
GAMMA 18 GAMMA 17 GAMMA 16 GAMMA 15 GAMMA 14 GAMMA 13 GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
GND
GND
Figure 25. Typical Application Circuit
Rev. 0 | Page 14 of 16
04614-025
ADD8708 TAP POINT AND REGULATOR VOLTAGE REQUEST FORM
REGULATOR SECTION--VREG OUT
To ensure correct regulator operation VDD must exceed VREG by 600 mV minimum--that is, a VREG = 14.4 V requires a minimum VDD = 15.0 V.
Parameter VREG OUT Value (6.9 V - 15.4 V)
TAP POINT SECTION
Gamma output voltages are calculated using the following formula:
VOUT =
TP x VREG OUT 500
A Microsoft(R) Excel spreadsheet is available which automatically calculates the best tap point based on VREG OUT and the desired output voltages for each gamma output.
Output VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 Tap Point
CUSTOMER INFORMATION
Name: Company: Address: ____________________________________________ ____________________________________________ ____________________________________________ ____________________________________________ Date: ____________________________________________
Please return this form to your local sales office.
Rev. 0 | Page 15 of 16
ADD8708 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 26. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body (CP-48) Dimensions shown in millimeters
0.75 0.60 0.45
1.60 MAX
48 1
9.00 BSC SQ
37 36
PIN 1
SEATING PLANE
1.45 1.40 1.35 10 6 2 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
TOP VIEW
(PINS DOWN)
7.00 BSC SQ
VIEW A
12 13 24 25
0.15 0.05
SEATING PLANE
0.50 BSC
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 27. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADD8708WCPZ-REEL72 ADD8708WSTZ-REEL2 Temperature Range -40C to +105C -40C to +105C Package Description 48-Lead Lead Frame Chip Scale Package 48-Lead Low Profile Quad Flat Package Package Option CP-48 ST-48
1 2
Available in reels only. Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04614-0-10/04(0)
Rev. 0 | Page 16 of 16

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